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1. ÐèÇóÆÊÎö£º´ÓÆóÒµÕæÊµ³¡¾°²ð½âÄ¿µÄ

ÐÐÒµÐèÇóµ÷ÑУºÁ¬Ïµ»ªÎª¡¢ÖÐÐ˵ÈÏàÖúÆóÒµµÄFPGA¸ÚλÐèÇó £¬£¬£¬Ã÷È·½¹µã¼¼ÄÜ£¨ÈçVerilog±à³Ì¡¢Ê±ÐòÔ¼Êø¡¢¸ßËÙ½Ó¿ÚÉè¼Æ£©¡£¡£¡£¡£¡£

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2. Ô­Ã÷ȷ˵£ºÓÃÉúÑÄ»¯±ÈÓ÷½µµÍÁýͳÃż÷

Ó²¼þÔ­Àí¿ÉÊÓ»¯£º

  • Óá°Ê³ÌÃ½ÐºÅÆ÷¡±±ÈÓ÷ʱÖÓÐźţ¨Ê±ÖÓÑØ´¥·¢Êý¾Ý¸üУ© £¬£¬£¬Óá°¿ìµÝ·Ö¼ðÖÐÐÄ¡±Àà±ÈFPGAÄÚ²¿Âß¼­µ¥Î»£¨CLB£©µÄ²¢Ðд¦Öóͷ£ÄÜÁ¦¡£¡£¡£¡£¡£
  • ͨ¹ý¶¯»­ÑÝʾFPGA¼Ü¹¹£¨²éÕÒ±íLUT¡¢´¥·¢Æ÷¡¢²¼Ïß×ÊÔ´£© £¬£¬£¬Á¬ÏµXilinx Artix-7¿ª·¢°åʵÎïͼ £¬£¬£¬Ö±¹ÛÃ÷È·¡°¿É±à³ÌÂß¼­¡±µÄʵÖÊ¡£¡£¡£¡£¡£

Êý×ֵ緽¹µã¿´·¨£º

  • ×éºÏÂß¼­£¨Èç¶à·ѡÔñÆ÷£©£ºÓá°½»Í¨Ñ¶ºÅµÆÇл»¡±°¸Àý½â˵ÊäÈëÊä³öʵʱӳÉä¹ØÏµ£»£»£»£»£»
  • ʱÐòÂß¼­£¨Èç¼ÆÊýÆ÷£©£ºÁ¬Ïµ¡°Ãë±í¼ÆÊ±¡±ËµÃ÷ʱÖÓͬ²½Óë״̬¼á³Ö»úÖÆ¡£¡£¡£¡£¡£
FPGAÈëÃÅ×÷Óý¼Æ»®Á÷³Ìͼ
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¿ìµÝ·Ö¼ðÖÐÐÄÀà±ÈFPGAÂß¼­µ¥Î»Ê¾Òâͼ
Xilinx Artix-7¿ª·¢°åʵÎïͼ
LEDÁ÷Ë®µÆ´úÂëʾÀýÓë×¢ÊÍ
ModelSim·ÂÕæ²¨ÐÎͼ
Vivado¹¤¾ßÁ´²Ù×÷½çÃæ½ØÍ¼

3. ´úÂë½â˵Óë×¢ÊÍ£º´Ó¡°Óï¹æÔòÔò¡±µ½¡°Ó²¼þÓ³É䡱

Verilog½ÌѧÈý²½·¨£º

  1. Óï·¨»ù´¡£ºÍ¨¹ý¡°Óë·ÇÃÅÉè¼Æ¡±½â˵module½ç˵¡¢assignÒ»Á¬¸³Öµ £¬£¬£¬Ç¿µ÷¡°Ó²¼þ²¢ÐÐÐÔ¡±ÓëÈí¼þµÄÇø±ð£¨Èç×èÖ¹forÑ­»·ÀÄÓã©£»£»£»£»£»
  2. Ä£¿£¿£¿£¿£¿£¿éʵս£ºÒÔ¡°LEDÁ÷Ë®µÆ¡±ÎªÀý £¬£¬£¬ÖðÐÐ×¢ÊÍ´úÂ빦Ч£º
module led_flow(
    input clk,       // ϵͳʱÖÓ£¨50MHz£©
    input rst_n,     // ¸´Î»Ðźţ¨µÍµçƽÓÐÓã©
    output reg [3:0] led  // 4λLEDÊä³ö
);
reg [23:0] cnt;  // ¼ÆÊýÆ÷£¬£¬£¬ÓÃÓÚ·ÖÆµ£¨50MHz¡ú2Hz£©
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) cnt <= 0;  // ¸´Î»Ê±¼ÆÊýÆ÷ÇåÁã
    else cnt <= cnt + 1;  // ʱÖÓÉÏÉýÑØ¼ÆÊý
end
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) led <= 4'b0001;  // ³õʼ״̬£ºµÚÒ»¸öLEDÁÁ
    else if(cnt == 24'd25_000_000) begin  // 0.5ÃëÇл»Ò»´Î
        led <= {led[2:0], led[3]};  // ×óÒÆ²Ù×÷£¬£¬£¬ÊµÏÖÁ÷ˮЧ¹û
    end
end
endmodule
  1. ¹ýʧ°¸ÀýÆÊÎö£ºÕ¹Ê¾¡°ÒÅÍü¸´Î»Ðźŵ¼ÖÂÉϵç״̬²»È·¶¨¡±¡°ÛÕ±Õ¸³Öµ£¨=£©Óë·ÇÛÕ±Õ¸³Öµ£¨<=£©»ìÓÃÒý·¢Ê±Ðò¹ýʧ¡±µÈ³£¼ûÎÊÌâ £¬£¬£¬ÅäºÏ²¨ÐÎͼ±ÈÕÕ׼ȷÓë¹ýʧЧ¹û¡£¡£¡£¡£¡£

4. ·ÂÕæÑéÖ¤£ºÓÃModelSim¹¹½¨¡°ÐéÄâʵÑéÊÒ¡±

Testbench±àд£º
Ϊ¡°LEDÁ÷Ë®µÆ¡±±àд·ÂÕæ¼¤Àø £¬£¬£¬Ä£ÄâʱÖÓ¡¢¸´Î»ÐźŠ£¬£¬£¬²¢¼à²âLEDÊä³ö£º

module tb_led_flow;
reg clk;
reg rst_n;
wire [3:0] led;
led_flow uut(.clk(clk), .rst_n(rst_n), .led(led));
initial begin
    clk = 0; forever #10 clk = ~clk;  // ÌìÉú50MHzʱÖÓ£¨ÖÜÆÚ20ns£©
end
initial begin
    rst_n = 0; #200 rst_n = 1;  // ¸´Î»200nsºóÊÍ·Å
    #1000000 $finish;  // ·ÂÕæ1msºó¿¢ÊÂ
end
endmodule

²¨ÐÎͼÆÊÎö£º
ͨ¹ýModelSimÊÓ²ìcnt¼ÆÊýÆ÷ת±äÓëled״̬Çл»µÄ¶ÔÓ¦¹ØÏµ £¬£¬£¬ÑéÖ¤¡°Ã¿0.5Ãë×óÒÆÒ»´Î¡±µÄÂß¼­ÊÇ·ñ׼ȷ £¬£¬£¬Öصã±êעʱÖÓÑØÓëÊý¾Ý¸üеÄʱÐò¹ØÏµ¡£¡£¡£¡£¡£

5. Éϰåµ÷ÊÔ£º´Ó¡°ÐéÄâ·ÂÕæ¡±µ½¡°Ó²¼þÂ䵨¡±

¿ª·¢¹¤¾ßÁ´²Ù×÷£º
ʹÓÃVivadoÍê³É¡°¹¤³Ì½¨Éè¡ú×ۺϣ¨Synthesis£©¡úʵÏÖ£¨Implementation£©¡úÌìÉú±ÈÌØÁ÷£¨Bitstream£©¡±È«Á÷³Ì £¬£¬£¬½â˵¡°Ê±ÐòÔ¼Êø¡±£¨ÈçÉèÖÃÊäÈëÊä³öÑÓ³Ù£©¶ÔÓ²¼þÎȹÌÐÔµÄÓ°Ïì¡£¡£¡£¡£¡£

°å¼¶µ÷ÊÔ¼¼ÇÉ£º

  • ÓÃILA£¨¼¯³ÉÂß¼­ÆÊÎöÒÇ£©×¥È¡ÊµÊ±ÐźŠ£¬£¬£¬¶¨Î»¡°°´¼üÏû¶¶²»³¹µ×¡±¡°µç»úÇý¶¯ÐźÅÑÓ³Ù¡±µÈÓ²¼þÎÊÌ⣻£»£»£»£»
  • Á¬ÏµXilinx ECO¿ª·¢°åµÄLED¡¢°´¼üµÈÍâÉè £¬£¬£¬Í¨¹ý¡°·ÖÄ£¿£¿£¿£¿£¿£¿é²âÊÔ¡úÁªµ÷¡±Öð²½Ñé֤ϵͳ¹¦Ð§¡£¡£¡£¡£¡£

¶þ¡¢ÊµÕ½°¸Àý£ºÖÇÄÜÑ­¼£Ð¡³µÏîĿȫÁ÷³Ì

1. ÐèÇóÆÊÎö

  • ¹¦Ð§Ä¿µÄ£ºÐ¡³µÍ¨¹ýºìÍâ´«¸ÐÆ÷ʶ±ðÐþÉ«¹ì¼£ £¬£¬£¬×Ô¶¯¾ÀÕýÆ«Ïò²¢¼á³Öǰ½ø £¬£¬£¬ÊµÏÖËÙÂʱջ·¿ØÖÆ¡£¡£¡£¡£¡£
  • ¼¼Êõ²ð½â£º´«¸ÐÆ÷Êý¾ÝÊÕÂÞ£¨ADC½Ó¿Ú£©¡¢PIDË㷨ʵÏÖ£¨Verilog״̬»ú£©¡¢µç»úÇý¶¯£¨PWMÄ£¿£¿£¿£¿£¿£¿é£©¡£¡£¡£¡£¡£

2. Ô­Ã÷ȷ˵

  • ´«¸ÐÆ÷Ô­Àí£ººìÍâ¶Ô¹Ü¡°·¢Éä-ÎüÊÕ¡±Ç¿¶ÈÓë¾àÀëµÄ¹ØÏµ £¬£¬£¬Óá°ÊÖµçͲÕÕÉä²î±ðÑÕÉ«ÎïÌåµÄ·´Éä²î±ð¡±Àà±È£»£»£»£»£»
  • PID¿ØÖÆ£ºÒÔ¡°¼ÝÊ»Æû³µÐÞÕýÆ«Ïò¡±±ÈÓ÷±ÈÀý£¨P£©¡¢»ý·Ö£¨I£©¡¢Î¢·Ö£¨D£©µÄ×÷Óà £¬£¬£¬Á¬Ïµ¹«Ê½ÍƵ¼²ÎÊýÕû¶¨Âß¼­¡£¡£¡£¡£¡£

3. ´úÂëʵÏÖ

  • ½¹µãÄ£¿£¿£¿£¿£¿£¿éʾÀý£¨PID¿ØÖÆÆ÷£©£º
module pid_controller(
    input clk,
    input rst_n,
    input [11:0] error,  // ¹ì¼£Îó²î£¨´«¸ÐÆ÷²îÖµ£©
    output reg [9:0] pwm_out  // µç»úPWMÕ¼¿Õ±È
);
reg [11:0] integral, derivative;
reg [11:0] error_prev;  // ÉÏÒ»ÖÜÆÚÎó²î
parameter Kp=5, Ki=1, Kd=2;  // ¿ØÖƲÎÊý
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        integral <= 0;
        derivative <= 0;
        error_prev <= 0;
    end else begin
        integral <= integral + error;  // »ý·ÖÏîÀÛ¼Ó
        derivative <= error - error_prev;  // ΢·ÖÏî=Ä¿½ñÎó²î-ÉÏÒ»Îó²î
        error_prev <= error;
        pwm_out <= Kp*error + Ki*integral + Kd*derivative;  // PIDÊä³ö
    end
end
endmodule

4. ·ÂÕæÑéÖ¤

  • ·ÂÕæ³¡¾°£ºÄ£Äâ´«¸ÐÆ÷¼ì²âµ½¹ì¼£×óÆ«¡¢ÓÒÆ«¡¢¾ÓÖÐÈýÖÖÇéÐÎ £¬£¬£¬ÊÓ²ìPWMÊä³öÊÇ·ñ°´Ô¤ÆÚµ÷½â£¨Èç×óƫʱÓÒ²àµç»úPWMÔö´ó £¬£¬£¬¾ÀÕýÆ«Ïò£©¡£¡£¡£¡£¡£

5. Éϰåµ÷ÊÔ

  • Ó²¼þÅþÁ¬£º½«´«¸ÐÆ÷Ä£¿£¿£¿£¿£¿£¿é¡¢µç»úÇý¶¯°åÓëFPGA¿ª·¢°åͨ¹ýGPIO½Ó¿ÚÅþÁ¬ £¬£¬£¬Ê¹ÓöŰîÏß°´µç·ԭÀíͼ½ÓÏߣ»£»£»£»£»
  • ÎÊÌâÅŲ飺ÈôС³µÆ«Àë¹ì¼£ £¬£¬£¬Í¨¹ýILAץȡerrorÐźŲ¨ÐÎ £¬£¬£¬·¢Ã÷´«¸ÐÆ÷²ÉÑùÑÓ³Ù £¬£¬£¬ÐèÔÚ´úÂëÖмÓÈëÊý¾Ý»º´æÄ£¿£¿£¿£¿£¿£¿éÓÅ»¯¡£¡£¡£¡£¡£

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  2. Ïòµ¼»úÖÆ£º1V1ÏßÉÏ´ðÒÉ£¨2СʱÄÚÏìÓ¦£©¡¢Ã¿ÖÜÖ±²¥¸´ÅÌ£¨Õë¶Ô¹²ÐÔÎÊÌâ½â˵£©£»£»£»£»£»
  3. ÉóºËÈÏÖ¤£ºÍê³ÉÏîÄ¿ºó½ÒÏþFPGA³õ¼¶¹¤³Ìʦ֤Êé £¬£¬£¬ÓÅÒìѧԱ¿ÉÄÚÍÆÖÁÏàÖúÆóÒµ¡£¡£¡£¡£¡£

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